meeting date: 01 nov 2005
attending: Arpad Muranyi, Ian Dodd, Todd Westerhoff, Mike LaBonte
           Bob Ross, Ken WIllis, Shang Li
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Review of ARs:

AR: Mike will annotate library modules
- XML files, PERL scripts, almost done

AR: Ken write simple receiver template
- done

AR: Ian will draft a BIRD for analog-only AMS support in IBIS
- In progress

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Simple receiver
- Based on EQ amp rcvr template

AR: Mike fix EQ amp rcvr template

Draft BIRD
- Ian working with Arpad
  - Will support Verilog-AMS, but allow for A/D and D/A
  - specify required lo/hi V, and dt for analog inputs
  - lo/hi V for analog output
- Discussion with Mentor analog sim people
  - No Verilog support in SI tools
  - Positive feedback so far
  - Analog portion of Verilog is fuzzy
    - 1999 standard, System-Verilog, etc.
- Ken unable to contact Cadence people yet
  - Positive feedback so far
- Current macro library would be illegal under current IBIS
- BIRD probably ready in 2 weeks

AR: Ian will draft a BIRD for analog-only AMS support in IBIS

PWL extrapolation policy
- SE = slope extrapolation
- HE = horizontal extrapolation
- extrapolation option:
  - On gives SE
  - Off gives error messages
- V/T tends to be HE, everything else SE
- Can always flatten the ends in case SE is used
- flexibilty vs. compatibility
- Use HE for dependent-V, SE for all else?
  - no, some dependent sources not ready for that
- IBIS parser assumes SE of I/V curves
- PWL VA code could check last 2 points at initialization
- For tool compatibility
- Not converging on this ...

AR: Mike add extrapolation warning to module documentation

Param arrays
- Cadence simulation is problematic
- HSPICE has same problem
- Re-write so tools can consume directly?
- Can cut & paste inot model instead of using external
  - PERL script could do it

Triggerable source
- Earlier decision was to do this later
- Arpad running into it now
- Tlsim is the only implementation

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Next meeting: Tuesday 08 nov 2005 (Mike can't make it).